1. Field of the Invention
Embodiments of the invention relate to chip-scale packages (CSPs), stacking integrated such CSPs in a multi-chip module (MCM) structure in a package-on-package (POP) configuration, and methods of forming such packages and structures.
2. Discussion of Related Art
Semiconductor dice are conventionally packaged individually in transfer-molded resin packages or, less commonly, ceramic packages. Packaging supports, protects, and (in some instances) dissipates heat from the semiconductor die and provides a lead system for power and ground or bias, as well as signal distribution to and from the semiconductor die or dice within. The die package may also facilitate burn-in and other testing of each semiconductor die or dice in the package prior to and after its assembly with higher-level packaging.
One type of integrated circuit (IC) or semiconductor die package is referred to as a “chip-scale package,” “chip-size package,” or merely “CSP.” These designations relate to the physical dimensions of the package, which are only nominally larger than the actual dimensions (length, width, and height) of the unpackaged semiconductor die. Chip-scale packages may be fabricated in “uncased” or “cased” configurations. Uncased chip-scale packages do not include encapsulation or other covering of the sides of a semiconductor die extending between the active surface and back side thereof, and thus exhibit a “footprint” (peripheral outline) that is substantially the same as that of an unpackaged semiconductor die. Cased chip-scale packages have encapsulated or otherwise covered sides and thus exhibit a peripheral outline that is slightly larger than that of an unpackaged semiconductor die. For example, a surface area of a footprint for a conventional cased chip-scale package may be up to about 1.2 times that of the bare semiconductor die contained within the package.
A chip-scale package may include an interposer substrate bonded to a surface of the semiconductor die. The interposer substrate conventionally includes traces extending to contacts for making external electrical connections to the semiconductor die of the chip-scale package. The interposer substrate for a chip-scale package may conventionally comprise a flexible material, such as a polymer (i.e., polyimide) tape such as KAPTON® tape, or a rigid material, such as silicon, ceramic, glass, BT (Bismaleimide Triazine) resin, or an FR-4 or other fiberglass laminate. The external contacts for one type of chip-scale package include solder balls or other discrete conductive elements protruding from the package and arranged in an array. Such a design is termed a “ball grid array” (BGA), or a “fine ball grid array” (FBGA) for such an array configuration having a very closely spaced, or pitched, array of discrete conductive elements. BGA and FBGA packaging provides the capability for a high number of inputs and outputs (I/Os) for a chip-scale package, several hundred I/Os being easily achieved if necessary or desirable.
Integrated circuit packaging surface mount technology, such as so-called “vertical surface mount packages” or “VSMP” technology, has also provided an increase in semiconductor die density on a single carrier substrate, such as a circuit board, as the die packages are mounted transverse to the plane of the carrier substrate. This configuration results in more compact designs and form factors and a significant increase in integrated circuit density. However, many VSMP designs are somewhat costly to implement and require fairly complex and sophisticated carrier substrates. In addition, for some applications, the relatively large distance of protrusion of the VSMPs above the carrier substrate is unacceptable for compact applications where vertical height is an issue and, for other applications unacceptably limits the number of carrier substrates which may be inserted transversely in adjacent slots of a higher-level packaging substrate, such as a PC motherboard.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the volume and thus cost of components used in packaging tends to decrease due to advances in packaging technology, even though the functionality (memory capacity and speed, processor speed, etc.) of the packaged end products increase. For example, on average there is approximately a ten percent decrease in packaging component volume for every product generation, as compared to the previous generation exhibiting equivalent functionality.
Chip-scale packages are thus of current interest in modern semiconductor packaging as a method for reducing both package size and cost. Further, the industry has responded to the limited space or “real estate” available for mounting semiconductor dice on a carrier substrate by vertically stacking two or more semiconductor dice, the I/Os of the die stack connecting to the carrier substrate often being provided between the lowermost semiconductor die and carrier substrate within the footprint of the stack. Therefore, it would be advantageous to provide a method and apparatus that may further reduce chip-scale package size and enhance robustness and heat transfer capabilities of the package while at the same time reduce fabrication cost and enhance production flexibility in combination with providing a capability to stack two or more semiconductor dice of the same or different types to increase circuit density on a carrier substrate to which such a multi-die chip-scale package is attached.